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Sc has been employed as an electron contact to a number of two-dimensional (2D) materials (e.g. MoS₂, black phosphorous) and has enabled, at times, the lowest electron contact resistance. However, the extremely reactive nature of Sc leads to stringent processing requirements and metastable device performance with no true understanding of how to achieve consistent, high-performance Sc contacts. In this work, WSe₂transistors with impressive subthreshold slope (109 mV dec⁻¹) andI_ON/I_OFF(10⁶) are demonstrated without post-metallization processing by depositing Sc contacts in ultra-high vacuum (UHV) at room temperature (RT). The lowest electron Schottky barrier height (SBH) is achieved by mildly oxidizing the WSe₂in situbefore metallization, which minimizes subsequent reactions between Sc and WSe₂. Post metallization anneals in reducing environments (UHV, forming gas) degrade theI_ON/I_OFFby ~10³and increase the subthreshold slope by a factor of 10. X-ray photoelectron spectroscopy indicates the anneals increase the electron SBH by 0.4–0.5 eV and correspondingly convert 100% of the deposited Sc contacts to intermetallic or scandium oxide. Raman spectroscopy and scanning transmission electron microscopy highlight the highly exothermic reactions between Sc and WSe₂, which consume at least one layer RT and at least three layers after the 400 °C anneals. The observed layer consumption necessitates multiple sacrificial WSe₂layers during fabrication. Scanning tunneling microscopy/spectroscopy elucidate the enhanced local density of states below the WSe₂Fermi level around individual Sc atoms in the WSe₂lattice, which directly connects the scandium selenide intermetallic with the unexpectedly large electron SBH. The interface chemistry and structural properties are correlated with Sc–WSe₂transistor and diode performance. The recommended combination of processing conditions and steps is provided to facilitate consistent Sc contacts to WSe₂.

The interconnect half‐pitch size will reach ≈20 nm in the coming sub‐5 nm technology node. Meanwhile, the TaN/Ta (barrier/liner) bilayer stack has to be >4 nm to ensure acceptable liner and diffusion barrier properties. Since TaN/Ta occupy a significant portion of the interconnect cross‐section and they are much more resistive than Cu, the effective conductance of an ultrascaled interconnect will be compromised by the thick bilayer. Therefore, 2D layered materials have been explored as diffusion barrier alternatives. However, many of the proposed 2D barriers are prepared at too high temperatures to be compatible with the back‐end‐of‐line (BEOL) technology. In addition, as important as the diffusion barrier properties, the liner properties of 2D materials must be evaluated, which has not yet been pursued. Here, a 2D layered tantalum sulfide (TaS_x) with ≈1.5 nm thickness is developed to replace the conventional TaN/Ta bilayer. The TaS_xultrathin film is industry‐friendly, BEOL‐compatible, and can be directly prepared on dielectrics. The results show superior barrier/liner properties of TaS_xcompared to the TaN/Ta bilayer. This single‐stack material, serving as both a liner and a barrier, will enable continued scaling of interconnects beyond 5 nm node.